The invention relates to a switching matrix of monolithic semiconductor device in which a number of PNPN type switching elements are formed on a single chip semiconductor by using a PN junction isolation technology.
Through the studying of a video switching system for exchanging a great deal of electrical signal information, it has been found that it is necessary to exchange analogue video signal or high speed digital signals at 100 Mb/s (Mega bits/second). This necessitates switching matrices capable of exchanging signals with wide frequency band in the order of 100 MHz, and such a necessity has triggered a pressing-need development of new signal switches. By convention, signal switches using switching elements of PNPN type are used for a switching matrix for a private branch exchange or a low speed digital signal exchange for computers. A dielectric isolation technology or an air isolation technology have been used for manufacturing the switching matrix, but it has scarcely been found that the PN junction isolation technology is used in the manufacturing of the switching matrix of monolithic semiconductor device. In such an electronic switching matrix, it is difficult to manufacture the one of high withstanding voltage, i.e. high maximum voltage level of the handling signal. Nevertheless, when it is used in the signal switch not requiring such a high withstanding voltage such as the video switching system, unlike the telephone switching system, there is no problem in practical use. Unfortunately, however, a conventional switching matrix of monolithic semiconductor device manufactured by the PN junction isolation technology suffers large signal crosstalk. The signal crosstalk is more remarkable as the frequency of it is higher. For this, the conventional switching matrix is impractical when it handles a signal of several MHz or more frequency. The following technics useful to improve the disadvantages have been known.
In U.S. Pat. No. 3,977,019, for example, there is disclosed a common collector darlington circuit using a P/P.sup.+ type double structure substrate to reduce the series resistance of the collector of the transistor formed therein.
In U.S. Pat. No. 3,760,239, the P type region is enclosed by the N.sup.+ type compensation region. Therefore, it is impossible to form a lateral type PNPN type switching element of the invention. The N.sup.+ compensation region also is used to isolate the elements from one another and to reduce the series resistance of the collector of the transistor.
A structure with the N.sup.+ type region enclosing the PNPN type switching element is described by A. R. Hartman and P. W. Shachle in an article "A Junction Technology for Integrating Silicon Controlled Rectifiers in Crosspoint Switching Circuits", IEDM 1976, page 55.